1. Field of the Invention
The present invention relates generally to methods for forming aperture fill layers within apertures within topographic substrate layers employed within microelectronics fabrications. More particularly, he present invention relates to methods for forming patterned planarized aperture fill layers within apertures within topographic substrate layers employed within microelectronics fabrications.
2. Description of the Related Art
Semiconductor integrated circuit microelectronics fabrications are formed from semiconductor substrates within and upon whose surfaces are formed semiconductor integrated circuit devices. The semiconductor integrated circuit devices are connected internally and externally to the semiconductor substrates upon which they are formed through the use of patterned conductor layers which are separated by dielectric layers.
As semiconductor integrated circuit microelectronics fabrication integration levels have increased and semiconductor integrated circuit device and patterned conductor layer dimensions have decrease, it has become more prevalent in the art of semiconductor integrated circuit microelectronics fabrication to employ isolation methods, such as but not limited to hallow trench isolation (STI) and recessed oxide isolation (ROI) methods to form patterned planarized trench isolation regions within isolation trenches within semiconductor substrates in order to separate active regions of the semiconductor substrates within and upon which are formed semiconductor integrated circuit devices.
Such shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods are desirable for forming patterned planarized trench isolation regions within isolation trenches within semiconductor substrates employed within semiconductor integrated circuit microelectronics fabrication since shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods typically provide patterned planarized trench isolation regions which are nominally co-planar with the surfaces of adjoining active regions of a semiconductor substrate which they separate. Such nominally planar patterned planarized trench isolation regions and adjoining active regions of a semiconductor substrate generally optimize utility of limited depth of focus typically achievable with an advanced photoexposure apparatus employed when forming advanced semiconductor integrated circuit devices and patterned conductor layers within an advanced semiconductor integrated circuit microelectronics fabrication.
Of the methods which may be employed to form patterned planarized shallow trench isolation (STI) regions within semiconductor substrates employed within semiconductor integrated circuit microelectronics fabrications, high density, plasma chemical vapor deposition (HDP-CVD) methods employed in conjunction with chemical mechanical polish (CMP) methods have recently received considerable attention. High density plasma chemical vapor deposition (HDP-CVD) methods are typically characterized as, and alternately known as, simultaneous chemical vapor deposition (CVD) and insert gas ion sputtering (typically argon ion sputtering) methods, where a ratio between a deposition rate within the chemical vapor deposition (CVD) method and removal rate within the inert gas ion sputtering method is controlled to bring about the net resultant rate of layer deposition often with specific desired layer properties.
While high density plasma chemical vapor deposition (HDP-CVD) methods undertaken in conjunction with chemical mechanical polishing (CMP) planarizing methods are thus desirable within the art of semiconductor integrated circuit microelectronics fabrication for forming patterned planarized trench isolation regions within isolation trenches within semiconductor substrates employed within advanced semiconductor integrated circuit microelectronics fabrications, patterned planarized trench isolation regions are often not formed entirely without problems within semiconductor integrated circuit microelectronics fabrications while employing high density plasma chemical vapor deposition (HDP-CVD) methods in conjunction with chemical mechanical polish (CMP) methods. In particular, it is often difficult to form, with optimal uniformity and planarity, a series of patterned planarized trench isolation regions within a series of isolation trenches separated by a series of mesas of varying width but substantially equivalent height within a semiconductor substrate while employing a high density plasma chemical vapor deposition (HDP-CVD) method in conjunction with a chemical mechanical polish (CMP) planarizing method as is conventional in the art of semiconductor integrated circuit microelectronics fabrication.
It is thus towards the goal of forming within a semiconductor integrated circuit microelectronics fabrication with optimal uniformity and planarity a series of patterned planarized trench isolation regions within a series of isolation trenches separated by a series of mesas of varying width but substantially equivalent height while employing a high density plasma chemical vapor deposition (HDP-CVD) method in conjunction with chemical mechanical polish (CMP) planarizing method that the present invention is more specifically directed in a more general sense, the present invention is also directed towards providing a method for forming within a microelectronics fabrication which need not necessarily be a semiconductor integrated circuit microelectronics fabrication, with optimal planarity and uniformity, a series of patterned planarized aperture fill layer within a series of apertures separated by a series of mesas of varying width, while employing a high density plasma chemical vapor deposition (HDP-CVD) method in conjunction with a chemical mechanical polish (CMP) planarizing method.
Various methods have been disclosed in the art of microelectronics fabrication for forming planarized aperture fill layers within apertures within topographic substrate layers employed within microelectronics fabrications.
For example, Avanzino et al., in U.S. Pat. No. 4,954,459, discloses a polishing planarizing method for forming a planarized aperture fill dielectric layer within an aperture, such as but not limited to an isolation trench, within a topographic substrate layer, such as but not limited to a semiconductor substrate, employed within semiconductor integrated circuit microelectronics fabrication. The method employs a conformal dielectric oxide layer formed over the topographic substrate layer, where upper lying portions of the conformal dielectric oxide layer corresponding with upper lying features of an underlying topography of the topographic substrate layer are selectively etched prior to a polish planarizing of the etched conformal dielectric oxide layer so formed.
Further, Bose et al., in U.S. Pat. No. 5,492,858, discloses a polish planarizing method for forming a planarized trench isolation region within an isolation trench of high aspect ratio within a semiconductor substrate employed within a semiconductor integrated circuit microelectronics fabrication. The method employs forming a silicon nitride trench liner layer within the isolation trench prior to forming within the isolation trench a conformal oxide dielectric layer which is subsequently steam annealed and polish planarized to form the planarized trench isolation region exhibiting enhanced properties.
Still further, Cooperman et al., in U.S. Pat. No. 5,494,897, discloses a planarizing method for forming a planarized shallow isolation trench region within a topographic semiconductor substrate employed in a semiconductor integrated circuit microelectronics fabrication. The method employs a pair of silicon oxide dielectric layers formed employing a chemical vapor deposition (CVD) method and separated by a layer of silicon where the upper lying silicon oxide dielectric layer and the silicon layer are subsequently chemical mechanical polish (CMP) planarized.
Finally, Gocho et l., in U.S. Pat. No. 5,498,565, discloses a high density plasma chemical vapor deposition (HDP-CVD) method in conjunction with a chemical mechanical polish (CMP) planarizing method for forming a series of patterned planarized trench isolation regions within a series of isolation trenches separated by a series of mesas of varying width within a semiconductor integrated circuit microelectronics fabrication. The method employs a masked isotropic etching of a portion of a comparatively thicker portion of a high density plasma chemical vapor deposited (HDPCVD) dielectric layer formed upon a wider mesa prior to chemical mechanical polish (CMP) planarizing the high density plasma chemical vapor deposited (HDP-CVD) dielectric layer.
Desirable within the art of microelectronics fabrication are additional high density plasma chemical vapor deposition (HDP-CVD) methods employed in conjunction with chemical mechanical polishing (CMP) planarizing methods which may be employed for forming within a topographic substrate layer employed within a microelectronics fabrication with optimal uniformity and planarity a series of patterned planarized aperture fill layers within a series of apertures separated by a series of mesas of varying width. More particularly desirable with the art of semiconductor integrated circuit microelectronics fabrication are additional high density plasma chemical vapor deposition (HDP-CVD) methods employed in conjunction with chemical mechanical polish (CMP) planarizing methods which may be employed for forming within a semiconductor substrate with optimal uniformity and planarity a series of patterned planarized trench isolation regions with a series of isolation trenches separated by a series of mesas of varying width.
It is towards the foregoing goals that the present invention is both generally and more specifically directed.